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MX29F4000
AUTOMATIC PROGRAMMING
The MX29F4000 is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29F4000 is less than 4 seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge of WE or CE, whichever happeds later, and data are latched on the rising edge of WE or CE, whichever happeds first. MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29F4000 electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 4 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29F4000 is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation.
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TABLE1. SOFTWARE COMMAND DEFINITIONS
First Bus Command Reset Read Read Silicon ID Sector Protect Verify Porgram Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Unlock for sector protect/unprotect Bus Cycle 1 1 4 4 4 6 6 1 1 6 Cycle Addr XXXH RA 555H 555H 555H 555H 555H XXXH XXXH 555H Data F0H RD AAH AAH AAH AAH AAH B0H 30H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 555H 90H ADI 02 555H A0H 555H 555H 80H 80H PA 555H 555H DDI 01H PD AAH AAH 2AAH 55H 2AAH 55H 555H 10H SA 30H 555H 90H (SA)X 00H Second Bus Cycle Addr Data Third Bus Cycle Addr Data Fourth Bus Cycle Addr Data Fifth Bus Cycle Addr Data Sixth Bus Cycle Addr Data
Note: 1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code A2-A18=Do not care. (Refer to table 3) DDI = Data of Device identifier : C2H for manufacture code, 99H for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA. 2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased. 3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 . Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A18 in either state. 4.For Sector Protect Verify Operation : If read out data is 01H, it means the sector has been protected.If read out data is 00H,it means the sector is still not being protected.
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 1 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device(when applicable).
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TABLE 2. MX29F4000 BUS OPERATION
Mode Read Silicon ID Manfacturer Code(1) Read Silicon ID Device Code(1) Read Standby Output Disable Write Sector Protect with 12V system(6) Chip Unprotect with 12V system(6) Verify Sector Protect with 12V system Sector Protect without 12V system (6) Chip Unprotect without 12V system (6) Verify Sector Protect/Unprotect without 12V system (7) Reset X X X X X X X HIGH Z L L H X H X H Code(5) L H L X X H H X L H L X X L H X L L H X H X VID(2) Code(5) L VID(2) L X X H VID(2) X L H L L L L X H H VID(2) H X H L L A0 X X A0 X A1 X X A1 X A6 X X A6 L A9 X X A9 VID(2) DOUT HIGH Z HIGH Z DIN(3) X L L H H L X VID(2) 99H Pins CE L OE L WE H A0 L A1 L A6 X A9 VID(2) Q0 ~ Q7 C2H
NOTES: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1. 2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V. 3. Refer to Table 1 for valid Data-In during a write operation. 4. X can be VIL or VIH. 5. Code=00H means unprotected. Code=01H means protected. A18~A16=Sector address for sector protect. 6. Refer to sector protect/unprotect algorithm and waveform. Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command. 7. The "verify sector protect/unprotect without 12V sysytem" is only following "Sector protect/unprotect without 12V system" command.
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READ/RESET COMMAND
The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verification command is required). If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the erase operation exceed internal timing limit. The automatic erase begins on the rising edge of the last WE or CE, whichever happeds first pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. The MX29F4000 contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 99H for MX29F4000.
TABLE 3. EXPANDED SILICON ID CODE
Pins Manufacture code Device code for MX29F4000 Sector Protection Verification
A0 VIL VIH X X
A1 VIL VIL VIH VIH
Q7 1 1 0 0
Q6 1 0 0 0
Q5 0 1 0 0
Q4 0 0 0 0
Q3 0 0 0 0
Q2 0 0 0 0
Q1 1 1 0 0
Q0 0 1 1 0
Code(Hex) C2H 99H 01H(Protected) 00H(Unprotected)
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SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE or CE, whichever happeds later, while the command(data) is latched on the rising edge of WE or CE, whichever happeds first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE or CE, whichever happeds later. Each successive sector load cycle started by the falling edge of WE or CE, whichever happeds later must begin within 30us from the rising edge of the preceding WE or CE, whichever happeds first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode.
Table 4. Write Operation Status
Status Q7 Note1 Byte Program in Auto Program Algorithm Auto Erase Algorithm Erase Suspend Read In Progress Erase Suspended Mode (Erase Suspended Sector) Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program Byte Program in Auto Program Algorithm Exceeded Auto Erase Algorithm Time Limits Erase Suspend Program Q7 Q7 0 Q7 Toggle Toggle Toggle Toggle 0 1 1 1 N/A N/A 1 N/A N/A No Toggle Toggle N/A Data Q7 0 1 Toggle Toggle No Toggle Data Data Data Data Q6 Q5 Note2 0 0 0 N/A 1 N/A No Toggle Toggle Toggle Q3 Q2
Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information.
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ERASE SUSPEND
This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended sectors. If the program opetation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode(no program verify command is required).
DATA POLLING-Q7
The MX29F4000 also features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data Polling feature is valid after the rising edge of the fourth WE or CE, whichever happeds first pulse of the four write pulse sequences for automatic program. While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data Polling feature is valid after the rising edge of the sixth WE or CE, whichever happeds first pulse of six write pulse sequences for automatic chip/ sector erase. The Data Polling feature is active during Automatic Program/Erase algorithm or sector erase time-out.(see section Q3 Sector Erase Timer)
ERASE RESUME
This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions.Another Erase Suspend command can be written after the chip has resumed erasing.
SET-UP AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Program mode, A three-cycle command sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Program command A0H. Once the Automatic Program command is initiated, the next WE or CE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE or CE, whichever happeds first pulse. The rising edge of WE or CE, whichever happeds first also begins the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin.
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Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happeds first pulse in the command sequence(prior to the program or erase operation), and during the sector timeout. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. Table 4 shows the outputs for Toggle Bit I on Q6. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 4 to compare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfuly completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. Toggle Bit I is valid after the rising edge of the final WE or CE, whichever happeds first pulse in the command sequence.
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Q5 Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition. If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector maynot be reused, (other sectors are still functional and can be reused). The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and powerdown transition or system noise.
Q3 Sector Erase Timer
After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
DATA PROTECTION POWER SUPPLY DECOUPLING
The MX29F4000 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND.
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SECTOR PROTECTION WITH 12V SYSTEM
The MX29F4000 features sector protection. This feature will disable both program and erase operations for these sectors protected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL.(see Table 2) Programming of the protection circuitry begins on the falling edge of the WE or CE, whichever happeds later pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes.(Read Silicon ID) It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector. It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.
POWER-UP SEQUENCE
The MX29F4000 powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.
SECTOR PROTECTION WITHOUT 12V SYSTEM
The MX29F4000 also feature a sector protection method in a system without 12V power suppply. The programming equipment do not need to supply 12 volts to protect sectors. The details are shown in sector protect algorithm and waveform.
CHIP UNPROTECT WITHOUT 12V SYSTEM CHIP UNPROTECT WITH 12V SYSTEM
The MX29F4000 also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode. To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE or CE, whichever happeds later, pulse and is terminated on the rising edge. The MX29F4000 also feature a chip unprotection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to unprotect all sectors. The details are shown in chip unprotect algorithm and waveform.
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CAPACITANCE (TA = 25oC, f = 1.0 MHz)
SYMBOL CIN1 CIN2 COUT PARAMETER Input Capacitance Control Pin Capacitance Output Capacitance MIN. TYP MAX. 8 12 12 UNIT pF pF pF CONDITIONS VIN = 0V VIN = 0V VOUT = 0V
READ OPERATION
DC CHARACTERISTICS (TA = 0 C TO 70 C, VCC = 5V10%)
SYMBOL ILI ILO ISB1 ISB2 ICC1 ICC2 VIL VIH VOL VOH1 VOH2 Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage(TTL) Output High Voltage(CMOS) 2.4 VCC-0.4 -0.3(NOTE 1) 2.0 Operating VCC current PARAMETER Input Leakage Current Output Leakage Current Standby VCC current 1 MIN. TYP MAX. 1 10 1 5 30 50 0.8 VCC + 0.3 0.45 UNIT uA uA mA uA mA mA V V V V V IOL = 2.1mA IOH = -2mA IOH = -100uA,VCC=VCC MIN CONDITIONS VIN = GND to VCC VOUT = GND to VCC CE = VIH CE = VCC + 0.3V IOUT = 0mA, f=5MH IOUT = 0mA, f=10MHz
NOTES: 1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns. 2. VIH max. = VCC + 1.5V for pulse width is equal to or less VIL min. = -2.0V for pulse width is equal to or less than 20 ns. than 20 ns. If VIH is over the specified maximum value, read operation cannot be guaranteed.
AC CHARACTERISTICS (TA = 0oC to 70oC, VCC = 5V10%)
29F4000-55(note2) 29F4000-70 29F4000-90 29F4000-12
Symbol PARAMETER tACC tCE tOE tDF tOH Address to Output Delay CE to Output Delay OE to Output Delay
MIN.
MAX. 55 55 30 30
MIN. MAX. MIN. MAX. MIN. MAX. Unit 70 70 40 0 0 NOTE: 30 0 0 90 90 40 40 0 0 120 120 50 40 ns ns ns ns ns
Conditions CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL
OE High to Output Float (Note1) 0 Address to Output hold 0
TEST CONDITIONS: * Input pulse levels: 0.45V/2.4V * Input rise and fall times is equal to or less than 0ns * Output load: 1 TTL gate + 100pF (Including scope and jig) * Reference levels for measuring timing: 0.8V, 2.0V
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1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2.Under condition of VCC=5V10%,CL=50pF,VIH/VIL=3.0/ 0V,VOH/VOL=1.5/1.5V,IOL=2mA,IOH=-2mA.
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ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & OE VALUE 0oC to 70oC -65oC to 125oC -0.5V to 7.0V -0.5V to 7.0V -0.5V to 7.0V -0.5V to 13.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change.
READ TIMING WAVEFORMS
VIH
Addresses
VIL
ADD Valid
tCE VIH
CE
VIL
WE
VIH VIL VIH VIL tACC tOH tOE tDF
OE
Outputs
VOH VOL
HIGH Z
DATA Valid
HIGH Z
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC CHARACTERISTICS (TA = 0oC to 70oC, VCC = 5V10%)
SYMBOL ICC1 (Read) ICC2 ICC3 (Program) ICC4 (Erase) ICCES NOTES: 1. VIL min. = -0.6V for pulse width is equal to or less than 20ns. 2. If VIH is over the specified maximum value, programming operation cannot be guranteed. 3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2. 4. All current are in RMS unless otherwise noted. VCC Erase Suspend Current 2 PARAMETER Operating VCC Current MIN. TYP MAX. 30 50 50 50 UNIT mA mA mA mA mA CONDITIONS IOUT=0mA, f=5MHz IOUT=0mA, F=10MHz In Programming In Erase CE=VIH, Erase Suspended
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AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10%
29F4000-55(Note2) 29F4000-70 SYMBOL PARAMETER
tOES tCWC tCEP tCEPH1 tCEPH2 tAS tAH tDS tDH tCESC tDF tAETC tAETB tAVT tBAL tCH tCS tVLHT tOESP tWPP1 tWPP2 OE setup time Command programming cycle WE programming pulse width WE programming pluse width High WE programming pluse width High Address setup time Address hold time Data setup time Data hold time CE setup time before command write Output disable time (Note 1) Total erase time in auto chip erase Total erase time in auto sector erase Total programming time in auto verify Sector address load time CE Hold Time CE setup to WE going low Voltge Transition Time OE Setup Time to WE Active Write pulse width for sector protect Write pulse width for sector unprotect 4(TYP.)
29F4000-90 MAX.
29F4000-12 MIN.
50 120 50 20 20 0 50 50 0 0
MIN.
50 70 45 20 20 0 45 30 0 0
MAX. MIN.
50 70 45 20 20 0 45 30 0 0 30 32 4(TYP.)
MAX. MIN.
50 90 45 20 20 0 45 45 0 0 30 32
MAX. Unit
ns ns ns ns ns ns ns ns ns ns 40 ns s s us us ns ns us us us ms
40 4(TYP.) 32 1.3(TYP.)10.4 7 100 0 0 4 4 10 12 210
4(TYP.) 32 1.3(TYP.)10.4 7 100 0 0 4 4 10 12 210
1.3(TYP.)10.4 7 100 0 0 4 4 10 12 210
1.3(TYP.) 10.4 7 100 0 0 4 4 10 12 210
NOTES: 1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2.Under conditions of VCC=5V10%,CL=50pF,VIH/VIL=3.0/0V,VOL/VOH=1.5/1.5, IOL=2mA,IOH=-2mA.
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MX29F4000
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST 1.6K ohm +5V
CL
1.2K ohm
DIODES=IN3064 OR EQUIVALENT
CL=100pF Including jig capacitance CL= 50pF for 29F4000-55
SWITCHING TEST WAVEFORMS
2.4V
2.0V 2.0V
TEST POINTS
0.8V
0.45V INPUT
0.8V OUTPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are < 20ns.(5ns for 29F4000-55) Note:VIH/VIL=3.0/0V,VOH/VOL=1.5/1.5V for 29F4000-55
COMMAND WRITE TIMING WAVEFORM
VCC
5V
Addresses
VIH
ADD Valid
VIL tAS tAH
WE
VIH VIL tOES tCEPH1 tCWC
tCEP
CE
VIH VIL tCS tCH
OE
VIH VIL VIH tDS tDH
Data
VIL
DIN
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MX29F4000
AUTOMATIC PROGRAMMING TIMING WAVEFORM
One byte data is programmed. Verify in fast algorithm and additional programming by external control are not required because these operations are executed automatically by internal control circuit. Programming completion can be verified by DATA polling and toggle bit checking after automatic verification starts. Device outputs DATA during programming and DATA after programming on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC PROGRAMMING TIMING WAVEFORM
Vcc 5V
A11~A18
ADD Valid
A0~A10 WE
555H
2AAH
555H
ADD Valid
tAS tAH
tCWC tCEPH1 tAVT tCESC
CE tCEP OE tDS Q0,Q1,Q2 Q4(Note 1) Q7
Command In Command #AAH (Q0~Q7) Command In Command #55H Command In Command #A0H Data In
tDH
Command In Command In Data In DATA
tDF
Command In
DATA polling
DATA DATA
tOE
Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit
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MX29F4000
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Toggle Bit Checking Q6 not Toggled YES
NO
Invalid Command
NO Verify Byte Ok YES NO Auto Program Completed Q5 = 1 YES
Reset
Auto Program Exceed Timing Limit
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MX29F4000
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM
Vcc 5V
A11~A18
A0~A10 WE
555H
2AAH
555H
555H
2AAH
555H
tAS tAH
tCWC tCEPH1
tAETC
CE tCEP OE tDS tDH Q0,Q1, Q4(Note 1) Q7
Command In Command #AAH Command In Command #55H Command In Command #80H Command In Command #AAH Command In Command #55H Command In Command #10H Command In Command In Command In Command In Command In Command In
DATA polling
(Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
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MX29F4000
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Toggle Bit Checking Q6 not Toggled YES
NO
Invalid Command
NO
DATA Polling Q7 = 1 YES
NO Auto Chip Erase Completed Q5 = 1
Reset
Auto Chip Erase Exceed Timing Limit
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REV. 1.0, DEC. 20, 1999
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MX29F4000
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector data indicated by A16 to A18 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Vcc 5V
A16-A18
Sector Address0
Sector Address1
Sector Addressn
A0~A10
555H tAS tAH
2AAH
555H
555H
2AAH tCWC
WE
tCEPH1 tBAL tAETB
CE
tCEP
OE
tDS tDH
Q0,Q1, Q4(Note 1)
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Command In
DATA polling
Q7
Command In
Command In
Command In
Command In
Command In
Command In
Command In Command #30H
Command In Command #30H
Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H (Q0~Q7)
Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
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MX29F4000
AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Toggle Bit Checking Q6 Toggled ?
NO Invalid Command
YES Load Other Sector Addrss If Necessary (Load Other Sector Address)
Last Sector to Erase YES
NO
Time-out Bit Checking Q3=1 ?
NO
YES NO
Toggle Bit Checking Q6 not Toggled YES
DATA Polling Q7 = 1
Q5 = 1
Auto Sector Erase Completed
Reset
Auto Sector Erase Exceed Timing Limit
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MX29F4000
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
NO Toggle Bit checking Q6 not toggled YES Read Array or Program
Reading or Programming End YES Write Data 30H
NO
Continue Erase
Another Erase Suspend ? YES
NO
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MX29F4000
TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V
A1
A6
12V 5V A9
tVLHT Verify
12V 5V OE
tVLHT tWPP 1 tVLHT
WE
tOESP
CE
Data
tOE
01H
F0H
A18-A16
Sector Address
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MX29F4000
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V
A1
12V 5V A9
tVLHT
A6
Verify
12V 5V OE
tVLHT tWPP 2 tVLHT
WE
tOESP
CE
Data
tOE
00H
F0H
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MX29F4000
SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
Set Up Sector Addr (A18, A17, A16)
PLSCNT=1
OE=VID,A9=VID,CE=VIL A6=VIL
Activate WE Pulse
Time Out 10us
Set WE=VIH, CE=OE=VIL A9 should remain VID
.
No
Read from Sector Addr=SA, A1=1
PLSCNT=32?
No
Data=01H?
Yes Device Failed
Protect Another Sector?
Yes
Remove VID from A9 Write Reset Command
Sector Protection Complete
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MX29F4000
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
Protect All Sectors
PLSCNT=1
Write "unlock for sector protect/unprotect" Command (Table 1)
Set OE=A9=VIH CE=VIL,A6=1
Activate WE Pulse to start Data do'nt care
No
Toggle bit checking Q6 not Toggled Yes Set OE=CE=VIL A9=VIH,A1=1 Increment PLSCNT
Set Up First Sector Addr
Read Data from Device No
Increment Sector Addr
Data=00H?
No
PLSCNT=1000?
Yes No
Yes Device Failed
All sectors have been verified? Yes Write Reset Command
Chip Unprotect Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
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REV. 1.0, DEC. 20, 1999
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MX29F4000
TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V OE
tCEP
WE
* See the following Note!
CE
Data
Don't care (Note 2) tOE
01H
F0H
A18-A16
Sector Address
Note1: Must issue "unlock for sector protect/unprotect" command before sector protection for a system without 12V provided. Note2: Except F0H
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MX29F4000
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V OE
tCEP
WE
* See the following Note!
CE
Data
Don't care (Note 2) tOE
00H
F0H
Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection for a system without 12V provided. Note2: Except F0H
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MX29F4000
SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for sector protect/unprotect" Command(Table1)
Set Up Sector Addr (A18, A17, A16)
OE=VIH,A9=VIH CE=VIL,A6=VIL
Activate WE Pulse to start Data don't care
Toggle bit checking Q6 not Toggled Yes Increment PLSCNT Set CE=OE=VIL A9=VIH
No .
No
Read from Sector Addr=SA, A1=1
PLSCNT=32?
No
Data=01H?
Yes Device Failed
Protect Another Sector?
Yes
Write Reset Command
Sector Protection Complete
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REV. 1.0, DEC. 20, 1999
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MX29F4000
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
Protect All Sectors
PLSCNT=1
Set OE=A9=VID CE=VIL,A6=1
Activate WE Pulse
Time Out 12ms
Increment PLSCNT
Set OE=CE=VIL A9=VID,A1=1
Set Up First Sector Addr
Read Data from Device No
Increment Sector Addr
Data=00H?
No
PLSCNT=1000?
Yes No
Yes Device Failed
All sectors have been verified? Yes Remove VID from A9 Write Reset Command
Chip Unprotect Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
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MX29F4000
ID CODE READ TIMING WAVEFORM
VCC
5V VID VIH VIL
VIH VIL tACC tACC
ADD A9
ADD A0 A1
VIH VIL
ADD A2-A8 A10-A18 CE
VIH VIL
VIH VIL
WE
VIH VIL
tCE
OE
VIH VIL
tOE tDF tOH tOH
VIH
DATA Q0-Q7
DATA OUT
VIL
DATA OUT 99H
C2H
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MX29F4000
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO. ACCESS TIME (ns) MX29F4000PC-55 55 MX29F4000PC-70 70 MX29F4000PC-90 90 MX29F4000PC-12 120 OPERATING CURRENT MAX.(mA) 30 30 30 30 STANDBY CURRENT MAX.(uA) 5 5 5 5 32 Pin PDIP (EPROM pinout) 32 Pin PDIP (EPROM pinout) 32 Pin PDIP (EPROM pinout) 32 Pin PDIP (EPROM pinout) PACKAGE
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MX29F4000
ERASE AND PROGRAMMING PERFORMANCE(1)
PARAMETER
Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles 100,000
MIN.
LIMITS TYP.(2)
1.3 4 7 4
MAX.(3)
10.4 32 210 12
UNITS
sec sec us sec Cycles
Note:
1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25 C,5V. 3.Maximunm values measured at 25C,4.5V.
LATCHUP CHARACTERISTICS
MIN. Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. -1.0V -1.0V -100mA MAX. 13.5V Vcc + 1.0V +100mA
DATA RETENTION
PARAMETER Data Retention Time MIN. 20 UNIT Years
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MX29F4000
REVISION HISTORY
Revision 1.0 Description 1.To remove "Advanced Information" datasheet marking and contain information on products in full production 2.The modification summary of Revision 0.1 & Revision 1.0: 2-1.Program/erase cycle times:10K cycles-->100K cycles 2-2.To add data retention 20 years 2-3.To modify timing of sector address loading period while operating multi-sector erase from 80us to 30us 2-4.To modify tBAL from 80us to 100us 2-5.To remove A9 from "timing waveform for sector protection for system without 12V" To remove A9 from "timing waveform for chip unprotection for system without 12V" Page P1 Date DEC/20/1999
P1,34 P1,34 P8 P15 P28 P29
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MX29F4000
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888 FAX:+886-3-578-8887
EUROPE OFFICE:
TEL:+32-2-456-8020 FAX:+32-2-456-8021
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TEL:+81-44-246-9100 FAX:+81-44-246-9105
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TEL:+65-747-2309 FAX:+65-748-4090
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TEL:+886-3-509-3300 FAX:+886-3-509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
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